HOME > 사업부소개 > 전자제품 사업본부
KFLV6 (PCB LVDS VCXO 14.4X9.6mm(6PAD)) 
 |
• Surface mount package 6PAD Design • Differential output PECL • Low Jitter • Available 3-state function • Mode : Fundamental, Multi |
| Standard Specification | ||||
|---|---|---|---|---|
| Frequency Range | 1.000MHZ to 65.000MHZ (Fund) | 0.75MHZ to 800.000MHZ (multi) | ||
| Supply voltage | 2.5V, 3.3V | |||
| Pin 1 Control voltage | 1.25V±1.05V (1.25V), 1.65V±1.35V (1.65V) | |||
| Frequency Deviation | ±100ppm min | |||
| Linearity | 10% max | |||
| Slope | Positive | |||
| Current consumption | 80㎃ max | |||
| Temperature Range | Operating | -40℃ to +85℃, User spec | ||
| Storage | -55℃ to +125℃ | |||
| Frequency Stability | ±50ppm max, User spec | |||
| Output load condition | 100Ω to Vdd-2.0V | |||
| Symmetry (Duty) | 45% to 55% | |||
| Output rise and fall time (tr/tf) | 1ns max (20% ~ 80% Ouput Level) | |||
| OE High / OE Low | 0.7Vdd min / 0.3Vdd max | |||
| High output voltage | 1.4V min | |||
| Low output voltage | 1.1V max | |||
| Pin 2 Input voltage | No Connection (Default) | |||
| Pin 2 Input voltage | 70% Vdd min (Output enable) | |||
| Pin 2 Input voltage | 30% Vdd max (Output disable) | |||
| Output Differential Voltage | 0.247V ~ 0.454V | |||
| Offset Voltage | 1.125V ~ 1.375V | |||
| Oscillation start up time | 5㎳ max | |||
| Aging | ± 3ppm max | |||
| phase Jitter (12KHZ ~20MHZ) | 1ps max | 4ps max | ||
